The company
The client is a Dutch technology innovator from Eindhoven. This iconic company is the hub of research and the mother of hi-tech companies in the region.

Role description
The ASIC team focuses on designing various mixed-signal Application-Specific ICs (ASICs) for biomedical applications. These CMOS ASICs typically handle sensor interfacing functions with substantial digital content. The candidate will participate in designing an ASIC for a novel and exciting application, joining a team of digital design engineers and working closely with the analog and mixed-signal teams. 

Responsibilities

• Collaborating with the analog and mixed-signal teams to design ASICs for biomedical applications.
• Translating potentially incomplete customer requirements into digital design specifications and proposals.
• Supporting digital verification and physical implementation activities.
• Specifying and integrating complex IP blocks and define integration baselines.
• Reporting progress and issues to the project leader and customer.
• Ensuring a good understanding of bus protocols and peripherals such as USB, SPI, I2C, and UART.
• Inserting DFT (Design for Test) including test-pattern generation.
• Engaging in daily interactions with the analog and mixed-signal teams. 

Requirements

• University Degree in Electrical Engineering.
• At least five years in digital design, verification, and top-level integration.
• Solid understanding of digital ASIC design flows, from architecture to RTL, digital and mixed-signal verification, design synthesis, physical implementation, and static timing analyses.
• Proficiency in VHDL, SystemVerilog, and preferably Python.
• Familiarity with DFT insertion and test-pattern generation.
• Basic knowledge of Mentor Graphics HDL Designer, Questasim, and Cadence Virtuoso for analog design is beneficial.
• Hands-on experience in digital backend is highly advantageous.
• Good to have – IC realization of DSP algorithms and functions for sensor interfacing applications, including digital filters, sample rate converters, and communication protocols.
• Good to have – Constraint random verification using SystemVerilog.
• Fluency in English. 

Other information 
Apply to our vacancy for more information. Looking forward to getting in touch!